1. Field of the Invention
The present invention relates to a semiconductor memory device called a DRAM and a method of operating the semiconductor memory device.
2. Description of the Prior Art
FIG. 1 shows a conventional stacked capacitor DRAM having a folded bit line arrangement. For the illustrative convenience, some of repetitive patterns are omitted in FIG. 1. In the DRAM, one memory cell is constituted by one access transistor 11 and one storage capacitor 12, and a word line WL1 serves as the gate electrode of the access transistor 11 in a memory cell X.
A storage node electrode 15 of the storage capacitor 12 is in contact with an n.sup.+ -type diffusion region 13 serving as one of the source and drain of the access transistor 11 through a contact hole 14. A bit line BL2 is in contact with an n.sup.+ -type diffusion region 16 serving as the other of the source and drain of the access transistor 11 through a contact hole 17 in the memory cell X.
In this prior art, as is apparent from FIG. 1, bit lines BL0, BL1, BL2, . . . extend in a direction connecting the diffusion regions 13 and 16, i.e., a y direction in FIG. 1, and word lines WL0, WL1, WL2, WL3, . . . extend in an x direction perpendicular to the y direction.
Since the memory device of the prior art has the folded bit line arrangement, portions of the word lines WL1 . . . located between the diffusion regions 13 and 16 and extending in the x direction are located on field insulation layers 21 between the memory cells adjacent to each other in the y direction. Therefore, the portions of the word lines WL1 . . . between the diffusion regions 13 and 16 serve as so-called select word line portions 22, and the portions of the word lines WL1 . . . on the field insulation layers 21 serve as so-called non-select word line portions 23.
When the two non-select word line portions 23 extend and are located between the memory cells adjacent to each other in the I direction as described above, not only the widths of the non-select word line portions 23 but the interval between the non-select word line portions 23 are required in the y direction. That is, since the lines and spaces of the non-select word line portions 23 are required in the Z direction, the sides of the memory cells cannot be easily decreased in length in the y direction.
In addition, since the bit lines BL2 . . . extend in the I direction, the bit lines BL2 . . . pass over the contact holes 14. For this reason, the storage capacitors 12 cannot be formed in the upper layer of the bit lines BL2 . . . , and the area of each of the storage capacitors 12 may be restricted with respect to the area of the corresponding memory cell. Due to the above reasons, in the prior art shown in FIG. 1, a memory cell area cannot be easily decreased, and a high integration level cannot be realized.
Note that an open bit line arrangement has no so-called non-select word line portion. However, in the folded bit line arrangement, stored data of a memory cell is output to only one of a pair of bit lines adjacent to each other, and no stored data is output to the other of the pair of bit lines. For this reason, the folded bit line arrangement has the following advantage and the like. That is, noise in a common mode is canceled by differentially operating a sense amplifier, and the sensitivity of the sense amplifier can be improved. However, the open bit line arrangement does not have the above advantages. Therefore, the open bit line arrangement cannot be employed.